Method and system to predict lithography focus error using simulated or measured topography

ABSTRACT

A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabrication,and more particularly, the present invention relates to lithographicprocesses used in semiconductor fabrication.

BACKGROUND OF THE INVENTION

Conventional optical projection lithography has been the standardsilicon patterning technology for many years. It is an economicalprocess due to its inherently high throughput, thereby providing adesirable low cost per part or die produced. A considerableinfrastructure (including steppers, photomasks, resists, metrology,etc.) has been built up around this technology.

In this process, a mask, or “reticle”, includes a device pattern formedof an opaque material, such as chrome, on a transparent orsemitransparent substrate. The transmission of the opaque material mayalso vary, such as in the case of an attenuating phase shift mask. Thedevice pattern of the reticle can be transferred to a photoresist filmusing imaging techniques well known in the art. For example, a stepperthat includes a light source and optics that project light comingthrough the reticle can be used to image the device pattern, often with,for example, a 4× to 5× reduction factor, onto a photoresist film. Thephotoresist can then be developed and used as a mask pattern forprocessing the device, as is well known in the art.

In photolithography, failing to achieve acceptable focus of the patternduring the imaging process can result in pattern defects, which cantranslate into device defects and possibly device failure. In somecases, the chip design itself can induce focus error. When the focuserror is unacceptably high, a chip redesign may be necessary, which is acostly and time-consuming endeavor. Therefore, it is desirable to have amethod and system for predicting lithography focus error that reducesthe need for chip redesign.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a method is provided forpredicting lithography focus error for a chip. The method comprisescomputing a focal plane that best fits a subset of chip topography data.Then, a minimal local residual of the focal plane is computed. Next, atotal focus error value is updated with the minimal local residual.Next, a new subset of chip topography data is acquired. These steps thenrepeat until each data point within the chip topography data isconsidered in at least one subset, resulting in the computation of afocus error value for the chip.

In another embodiment of the present invention, a system is provided forpredicting lithography focus error for a chip. The system comprises aprocessor and non-volatile memory. The processor is configured anddisposed to read executable instructions from the non-volatile memory.When these instructions are executed by the processor, the systemperforms various computational steps. First, a focal plane that bestfits a subset of chip topography data is computed. Next, a minimal localresidual of the focal plane is computed. In one embodiment, a leastsquares fit is used. Next, a total focus error is updated with theminimal local residual. In one embodiment, this is done with a movingaverage. Then, a new subset of chip topography data is acquired. Thesesteps are then repeated until each data point within the chip topographydata is considered in at least one subset, at which point, the totalfocus error is the focus error value for the chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart indicating process steps in accordance with anembodiment of the present invention.

FIG. 2 is a block diagram indicating data flow in accordance with anembodiment of the present invention.

FIG. 3 is a flowchart indicating process steps in accordance with anembodiment of the present invention.

FIG. 4 is a graphical representation of focus error in accordance withan embodiment of the present invention.

FIG. 5 is an additional graphical representation of focus error inaccordance with an embodiment of the present invention.

FIGS. 6A-6E show representations of simulated topography data.

FIG. 7 is a block diagram of a system in accordance with an embodimentof the present invention.

DETAILED DESCRIPTION

Topography refers to the variation in height (Z) above the surface of asubstrate. In semiconductor fabrication, typically a planarization step,such as a chemical mechanical polish (CMP) is performed to make thesurface of the substrate smooth, such that a subsequent layer of thesemiconductor can be formed. Typically, the first step in forming alayer of a multilayer integrated circuit (IC) is deposition of a masklayer, followed by a patterning step. Regions of the mask are cured viaa lithographic process. Lithography tools focus an image onto the masklayer to cure a portion of the mask, while other parts of the maskremain uncured. The result is a pattern that is used in formation ofsubsequent layers used in the semiconductor fabrication process.Ideally, the planarization step makes the substrate completely smooth.However, in practice, there are variations in height (Z variations) duein part to the differing material characteristics of the variousmaterials (e.g. polysilicon, metal, dielectric) undergoing the CMPprocess. If these Z variations are too great, then parts of thesubstrate will lie outside the focal plane of the lithography tool,which could result in patterning errors. If these errors are discoveredafter reticles have been created, the cost of such an error is quitehigh, as it may result in the need for a new reticle. It is thereforedesirable to detect such a condition during the design stage of a chip,rather than in the fabrication stage. By detecting it in the designstage, it allows the possibility for design modification prior to makingreticles, thereby saving considerable time and money.

FIG. 1 is a flowchart 100 indicating process steps in accordance with anembodiment of the present invention. In process step 102, simulatedtopography data is generated. This data represents a plurality of x-y-zdata points that together represent the height of the substrate atvarious points on a chip, relative to a base Z (height) reference level.In one embodiment, this data is received from the output of a CMPsimulation process. In process step 104, the estimated focus error iscomputed. This is done by computing a focal plane that best fits thetopography data, and setting the focal plane such that the residual(error) is minimized. In one embodiment, computing the focal plane thatbest fits a subset of the chip topography data comprises computing abest fit plane that minimizes the maximum distance from the points tothe plane. In another embodiment, a best fit plane is computed thatminimizes the sum of squared distances to the plane. In anotherembodiment, a least squares fit is used to compute the focal plane. In aspecific embodiment, a least squares fit regression plane is computed,in which case X and Y values are fixed, and the measured error is in theZ dimension alone.

The focus error is then compared against a predetermined threshold instep 106 to determine if the estimated focal error is at an acceptablelevel. A criterion for acceptability includes the CD (criticaldimension) for the particular layer. The CD is the size of the smallestfeature on the layer. The CD varies with the acceptability level. Forexample, if the CD is 75 nm (nanometers), there is a higher acceptablelimit of focal error than in the case of a CD of 40 nm. If the focuserror is acceptable, the process ends.

One of the inputs to the focus error estimation is a slit size. The slitsize (aperture size) controls the amount of light irradiated onto thesubstrate during the patterning process. The slit size controls atradeoff between exposure times and focus. If the estimated focal erroris not acceptable, based on the CD, then a different slit size may beused to perform the simulated focus error calculation. The slit sizerefers to the slit size used in a scanning lithography tool. If thefocal error is unacceptable with a particular slit size, then anotherslit size can be used as input to the focus error simulation in processstep 110. While any slit size can be used in a simulation, in practice,the variation in slit size is a function of the lithography tool. Hence,it is contemplated that for practical purposes, the variation in slitsize used for the simulations is within the range of the possible slitsizes for a particular lithography tool.

In process step 112, the resulting focus error from process step 110 iscompared against the predetermined threshold similar to that of processstep 106. If the focus error is acceptable, the process ends. If thefocus error is not acceptable, the chip layout is altered in processstep 114. The layout alteration may include modifying the position ofone or more functional areas (“chiplets”) within the chip to reduce theZ variation. The process then repeats, with a new simulated topographycalculated in process step 102, based on the new layout data resultingfrom process step 114. In process step 117, the number of retry attemptsis monitored, and if it exceeds a predetermined threshold, the processends. In this case, a more thorough chip re-design may be needed toaccount for lithographic issues.

FIG. 2 is a block diagram 200 indicating data flow in accordance with anembodiment of the present invention. In one embodiment, layout data 201is input to a CMP simulation process 202. Layout data 201 may comprisedata in a format of GDSII or OASIS. Other formats may also be used. Theoutput of CMP simulation process 202 is simulated topography data 204.Simulated topography data 204 is an input to the focus error estimationprocess 206, along with the slit size 205. The outputs of focus errorestimation process 206 may include, but is not limited to, a graphicalrepresentation 218, a design warning indication 214, and a slit sizerecommendation 216.

As an alternative to obtaining the simulated topography from CMPsimulation process 202, density data 208 is input into a densityapproximation process 210. Density approximation process 210 maycomprise a database of empirical relationships between density andtopography. In this context, density refers to the makeup of substratematerials at the surface within a particular logical area referred to asa “bounding region.” A bounding region is typically quite small incomparison to the size of a chip. Hence, there may be many thousands oreven millions of bounding regions within a chip. Within each boundingregion, the makeup of materials is considered. The percentage of metal,dielectric, polysilicon, and other materials within the bounding regionis contained within the density data 208. The density approximationprocess 210 outputs a simulated topography data set 212 based on thedensity data 208. That is, for each bounding region, an estimated Z(height) value is derived from the density (e.g. the metal density, suchas the ratio of metal to dielectric) within that region, thereby formingthe simulated topography data set 212. In addition to density data 208,geometry data 215 may also be considered when generating simulatedtopography data set 212. While in general, a density near the 50% areais preferable (e.g. approximately 50% metal and approximately 50%dielectric), geometry data may also be considered. Geometry data mayinclude, but is not limited to, the width of metal lines. By taking thegeometry into account, a more accurate simulation can be achieved.

For example, consider a case of alternating 25 micrometer metal linesand 25 micrometer spaces of dielectric, then the resulting density is50% and good lithography results can be inferred. However, consider asecond case of alternating 150 micrometer metal lines and 150 micrometerspaces of dielectric. In that case, the resulting density is still 50%.However, the wider lines are more prone to adverse CMP effects such asdishing, and hence an optimal lithography likely would not be achieved,even with the density at or near 50%. Hence, by considering both densityand geometry, more accurate topology results may be achieved. In oneembodiment, a width constraint may be used to prevent a simulatedtopography 212 that has features that are so large as to be prone todishing.

Simulated topography data set 212 is then input to the focus errorestimation process 206, and outputs 214, 216, and 218 may be output fromthe focus error estimation process 206 as described previously.Optionally, output 221 is provided, which is a chip layoutrecommendation for minimizing focus error. The layout recommendation isbased on the best chip layout tried in process step 114 of FIG. 1.

FIG. 3 is a flowchart 300 indicating process steps in accordance with anembodiment of the present invention. Flowchart 300 shows specificdetails of the focus error estimation process (see 206 of FIG. 2). Inprocess step 302, topography data is received. In process step 304, asubset of topography data is considered, the size of which, is dependenton a slit size for a lithography tool. In process step 306, a plane thatsatisfies the least squares fit of the subset of topography data iscomputed. In process step 308, a local residual (error) is computed. Inprocess step 310, a total residual (focus error) value is updated withthe value of the local residual. In one embodiment, the total residualvalue is computed as a moving average of the local residuals. In processstep 312 a check is made to determine if the last slit position has beenreached. If the last list position has not been reached, then in processstep 314, the slit is moved to the next position, which may entailshifting it by one pixel for each iteration. As this is a simulationprocess, there is no physical slit, but rather a selection of a newsubset of topography data based on the slit size for a lithography tool.The process steps starting with 306 continue until the last slitposition is reached, meaning that the entire exposure field has beenencompassed within at least one subset of topography data represented bythe slit. In process step 316, the focus error is computed as the totalresidual from step 310. In step 318 the focus error is presented to auser. The presentation may include, but is not limited to, a graphicalrepresentation of the error, and a textual representation of the error,which may further comprise a warning for the user if the focus error isdetermined to be unacceptably high at any location within the chip.

FIG. 4 is a graphical representation of focus error in accordance withan embodiment of the present invention. A graphical region 402represents an exposure field, which preferably includes an areacorresponding to a chip on a wafer. In graphical region 402, differentfocus error ranges are represented by different indicia. Within the chipare a plurality of regions (indicated generally as 404, for illustrativeclarity, only one such region is indicated with a reference number) anda legend 420 indicating the focus error pertaining to each region. Inone embodiment, the unit of measurement for the focus error isnanometers. While different patterns are shown for various regions 404in FIG. 4, it s also contemplated that different colors may be used torepresent various levels of focus error instead of, or in addition to,the use of patterns.

FIG. 5 is an additional graphical representation of focus error inaccordance with an embodiment of the present invention. A portion of arepresentation of a wafer 500 is shown in FIG. 5. The waferrepresentation 500 comprises a plurality of chip representations 502,each of which, are similar to 402 of FIG. 4. Note that while only a fewchip representations 502 are shown in FIG. 5, in practice, there may bethousands of such chip representations shown within wafer representation500. This graphical representation provides a way to identify recurringpatterns of focus error within a wafer.

FIG. 6A shows a representation of exemplary topography data 600.Topography data 600 comprises a plurality of data tuples (“datapoints”), indicated generally as 602. Each tuple includes, but is notnecessarily limited to, an X coordinate, a Y coordinate, and a Zcoordinate, where Z represents a height value above or below a baselevel of a semiconductor substrate. In the example shown in FIGS. 6A-6C,the data units are arbitrary. In practice, it is contemplated thatnanometers or angstroms may be used. Slit 606A defines a subset of datatuples that will be used for performing a least squares error fit forthe focal plane. As shown in FIG. 6A, the slit 606A encompasses thetuple <1,2, * >, where X=1, Y=2, and “*” represents any value for the Zdimension. The slit also encompasses the tuple <5, 3, *>. Hence, theslit 606A can be defined by the two endpoint tuples <1, 2, *> and <5, 3,*>. Note that while the slit 606A shown in FIG. 6A encompasses 10tuples, in practice, there may be many thousands of tuples (data points)within the region defined by a slit. In another embodiment, the tuplemay comprise a pair of X-Y coordinates that define an area referred toas a “tile.” The Z value of the tuple may be the average Z (height)within the tile. Alternatively, the worst-case Z value for the tile maybe used as the Z value of the tuple. In one embodiment, the tile size isa user-configurable parameter. For example, a tile size of 10 micronsmay yield more accurate results than a tile size of 50 microns, with thetradeoff being a longer execution time required to run the simulationfor a smaller tile size.

FIG. 6B shows the same topography data 600, but with the slit (indicatednow as 606B) moved to its next position, now defined by endpoint tuples<1, 3, *> and <5, 4, *>. This new slit position corresponds to processstep 314 shown in FIG. 3. The subset of tuples defined by slit 606B arethen used for performing a least squares error fit for the focal plane.This procedure is repeated as the slit is moved “over” the entire set oftopography data tuples (data points).

FIG. 6C shows the same topography data 600, but with the slit (indicatednow as 606C) of a different size than slit 606A (see FIG. 6A). In thiscase, slit 606C is larger than slit 606A of FIG. 6A. Slit 606C isdefined by the two endpoint tuples <1, 3, *> and <5, 5, *>.

Changing a slit from 606A to 606C corresponds to process step 108 inFIG. 1. In many cases, it may be preferable to use a different slitsize, which is a tool reconfiguration, if doing so can avoidunacceptable focus error, and also avoid the need to alter the chiplayout.

FIG. 6D shows a representation of exemplary topography data 616. In thisfigure, compensation for boundary conditions is shown, as slit 606D isat the topmost part of the chip (top chip boundary). When fitting aplane near the boundaries of a chip, a synthesized topology dataset canbe used to enable consistent plane-fitting calculations. In FIG. 6D, thetop row (Y=0) comprises synthesized topology dataset 625. In this case,the Z value for the synthesized topology dataset is set to “not anumber” (NaN). NaNs are part of the IEEE 754 floating-point standard,and are used to enable calculations that require particular sizedmatrices when insufficient real data exists. For example, mathcomputation programs such as MATLAB can utilize the NaN entries in thesynthesized topology dataset 625 to perform plane fitting at theboundaries.

FIG. 6E shows a representation of exemplary topography data 618. In thisfigure, an alternative method for compensation for boundary conditionsis shown. When fitting a plane near the boundaries of a chip, asynthesized topology dataset 635 is used to enable consistentplane-fitting calculations. However, instead of using NaN like dataset625 of FIG. 6D, synthesized topology dataset 635 uses estimated Z values(indicated as B1, B2, B3, B4, and B5). In practice, the values B1-B5 maybe set to expected values as if another identical chip was present atthat location. Hence, the synthesized topology dataset comprises valuesfrom areas opposite the location of the slit 606E. For example, in aboundary at the top of a chip, the Z values (B1-B5) may represent Z dataat the bottom of that chip, since if additional identical chips aresimulated around a particular chip, the bottom of one chip may beadjacent to the top of the chip undergoing the simulation.

FIG. 7 shows a block diagram of a system 700 in accordance with anembodiment of the present invention. System 700 comprises a computersystem 750 which comprises microprocessor 752, Random Access Memory(RAM) 756, and non-volatile memory (NV-MEM) 754. NV-MEM 754 comprisesmachine instructions, which may be organized into a plurality ofmodules. These modules may include, but are not limited to, focusestimation module 760, topology import module 762, and density map data764. Alternatively, all or part of these modules may be stored usinganother technology, such as a magnetic or optical disk drive, withoutdeparting from the scope and purpose of the present invention. Userinterface 768 may comprise, but is not limited to, a keyboard, a mouse,trackball, or other selection device, and a display for presenting thefocus error information to a user.

Although the invention has been shown and described with respect to acertain preferred embodiment or embodiments, certain equivalentalterations and modifications will occur to others skilled in the artupon the reading and understanding of this specification and the annexeddrawings. In particular regard to the various functions performed by theabove described components (assemblies, devices, circuits, etc.) theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (i.e., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary embodiments of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several embodiments,such feature may be combined with one or more features of the otherembodiments as may be desired and advantageous for any given orparticular application.

What is claimed is:
 1. (canceled)
 2. The method of claim 7, furthercomprising: changing the size of the subset of chip topography data, andrepeating steps a, b, c, and d, and identifying a subset size thatresults in the smallest focus error, wherein the subset size isrepresentative of a slit size.
 3. The method of claim 7, furthercomprising: changing the chip layout, receiving updated chip topography,the updated chip topography representative of the changed chip layout,and repeating steps a, b, c, and d, and identifying a chip layout thatresults in the smallest focus error.
 4. (canceled)
 5. (canceled)
 6. Themethod of claim 7, further comprising: wherein the step of deriving a Zvalue based on an empirical data further comprises: measuring topologysamples and corresponding density values.
 7. A method for predictinglithography focus error for a chip by analyzing chip topography data,comprising: a) computing a focal plane that best fits a subset of thechip topography data; b) computing a minimal local residual of the focalplane; c) updating a total focus error value with the minimal localresidual; d) acquiring a new subset of chip topography data; andrepeating steps a, b, c, and d until each data point within the chiptopography data is considered in at least one subset, thereby computinga focus error value for the chip; deriving the chip topography data fromchip density data; wherein the density data comprises the ratio of metalto dielectric material for a region within a chip; and deriving the chiptopography data from a CMP simulation.
 8. The method of claim 7, furthercomprising: providing a graphical region representing an exposure field,wherein different focus error ranges are represented by differentindicia.
 9. The method of claim 8, wherein the indicia comprisedifferent patterns.
 10. The method of claim 8, wherein the indiciacomprise different colors.
 11. The method of claim 7, furthercomprising: providing a graphical region representing a waferrepresentation, wherein the wafer representation comprises a pluralityof exposure field images, wherein each of the exposure field imagesindicates different focus error ranges as represented by differentindicia.
 12. The method of claim 7, wherein the subset of chiptopography data comprises a synthesized topology dataset.
 13. The methodof claim 12, wherein the synthesized topology dataset comprisesnot-a-number entries. 14-20. (canceled)